A conventional communication control apparatus employs a general-purpose communication control LSI, to execute serial transmission and reception under software control. Conventionally, a memory for storing transmit data and receive data is provided on the outside of the communication control LSI. However, there are many cases where the communication control LSI is formed by a communication control LSI which incorporates or builds therein a small-capacity RAM for storing therein the transmit data and the receive data, because the capacity of the transmit data and the capacity of the receive data are limited correspondingly to a particular application. A system arrangement which realizes the serial communication between the host control unit and the I/O control unit by the use of the above-described communication control LSI is shown in FIG. 10 of the attached drawings.
FIG. 10 is a view showing an arrangement of the conventional communication control apparatus. In FIG. 10, the reference numeral 1 denotes a host control unit; 2, an I/O control unit; 3, a serial-communication transmitting control section for various units; 4, a receiving control section of serial communication for various units; 5, a transmitting address counter for various units; 6, a transmitting data counter for various units; 7, a receiving address counter for various units; 8, a receiving data counter for various units; 9, a transmitting RAM for various units; 10, a receiving RAM for various units; 51, a host CPU of the host control unit 1; and 52, an I/O CPU of the I/O control unit 2.
Further, the reference numeral 701 denotes a data bus for connecting the transmitting RAM 9 for various units and the CPUs 51 and 52 for various units to each other; 702, a data bus for connecting the receiving RAM 10 for various units and the CPUs 51 and 52 to each other; 703, a command and status control line for connecting the CPUs 51 and 52 for various units and the transmitting control section 3 to each other; and 704, a command and status control line for connecting the CPUs 51 and 52 for various units and the receiving control section 4 to each other.
Operation will next be described. Using bus 701, the host CPU 51 writes the transmit data to the transmitting RAM 9, which is arranged within the host control unit 1. Then the transmitting control section 3 reads the transmitting data in terms of one word units and, on the basis of the values in counters 5 and 6, serially transmits the transmitting data. The serial data transmitted from the host control unit 1 are inputted to the receiving control section 4 on the side of the I/O control unit 2, and are successively written to the receiving RAM 10, on the basis of the values in counters 7 and 8. The written data are read by the I/O CPU 52. The same is applicable in a reverse direction.
Furthermore, if the above-described communication control system is applied to a numerical control apparatus, the communication control system takes an arrangement illustrated in FIG. 11. In the numerical control apparatus illustrated in FIG. 11, the data communication, and the preparation, analyzing and processing of the data communication, typically takes place between a servo amplifier unit 803 and the main-spindle amplifier unit (not shown), and an NC control unit 800. Generally, in such system, the communication speed is raised to shorten a communication cycle, by the addition of a motion control CPU 806 capable of processing the data at a high speed, because of the demands for operating the NC machine tool at high speed and high accuracy. Typically, when data is to be transmitted, a base register 15 receives a top or head address for a first frame and the subsequent addresses of the transmitted data frame are identified by an address counter 13, which inputs to the transmit RAM 12. The count of the data for each frame is determined on the basis of a base value of register 16 and a count from that value counter 14, serving as an input to control 11. A similar arrangement for storing plural frames of data on the basis of a head address on register 25 and a count therefrom in counter 23, together with a data base value in resister 26 and a counted value from operation of counter 24 is found to control the serial reception by receive RAM 22 and receive control 21.
The above-described motion control CPU 806 has principal or main processing which includes:
1 initial processing: initializing the processing of the serve amplifier unit 803 and the main-spindle amplifier unit; PA1 1 background processing: the preparation of transmit data and the analysis of received data to and from the servo-amplifier unit 803 and the main-spindle amplifier unit; PA1 1 servo-interruption processing: timing of the transmission to the servo-amplifier unit 803 and the main-spindle amplifier unit and reception from the servo-amplifier unit 803 and the main-spindle amplifier unit.
As another reference technical literature relating to the invention, there are "Receiving Unit For Serial Data" disclosed in Japanese Patent Laid-Open No. HEI 2-52543 and "Multi-Channel Multi-Frame Receiving Circuit" disclosed in Japanese Patent Laid-Open No. HEI 2-177737.
The conventional system has the following problems with reference of FIG. 11. First, there is only one transmitting address base register 15 in each unit (800, 803) which indicates a head or top address of the transmit data in the corresponding transmitting RAM 12. Accordingly, in order to transmit a plurality of frames per unit time, it is required that the CPU resets the top address of the transmitting data used in the subsequent transmitting frame at every point in time that transmission is initiated. The reset top address is needed, to execute processing in which the transmitting section for transmitting an actual transmitting frame restarts. This requirement applies a significant processing load on the CPU, and the processing software is complicated.
Moreover, there are the following problems. First, in the case where a plurality of frames are received, there is only one top-address retaining register 20 for the receiving RAM 22 for storing therein the receive data. Accordingly, in the case where the number of top receiving data bytes including the receiving frames varies by accident or error on the serial transmitting line, in other words, in the case where a length of the frame received previously is short or long when the plurality of frames are received, the receiving RAM storing addresses of the subsequent receiving data are located at different positions. For this reason, the top position in the receiving RAM of the received frame shifts so that the top position of the received frame must be searched for by software processing. Thus, processing due to the software is complicated, and processing time is lengthened.
Further, "Receiving Unit For Serial Data" disclosed in Japanese Patent Laid-Open No. HEI 2-52543 discloses an arrangement in which a plurality of frames are stored in the same memory. In this case, however, data-length information is included in the receiving frame. However, in the case where the data-length information is erroneously recognized by a receiving circuit, the normal receiving operation of a subsequent receiving frame cannot be assured, due to problems with the transmitting line.
A further problem involves the interrupt processing which is conducted at the expose of background processing. Specially, in the communication control system in the numerical control apparatus, interruption of the motion-control CPU 806 occurs with a variable cycle. Accordingly, the cycle is shortened in the case where a high speed and a high accuracy are required, and frequency of the servo-interruption processing increases. Accordingly, the time available for generation of the transmitting data and analysis of the receiving data is shortened.